an1434.pdf (827 KB)
an1725.pdf (1.12 MB)
isl55210.pdf (981 KB)
isla112p50.pdf (1.19 MB)
So let's move on now to see what kind of performance we're able to show with this lab setup. Since we have the capability on the board, let's look at the frequency response first, to make sure that it's flat to the region we care about, and also controls the bandwidth out of band. So what we show here is a network analyzer shot of the frequency response from board edge up to the ADC. Now, we've stored this trace, because we're actually taking FFTs right now also. But we can see a little bit of roll-off on the low end, and this is due to our input transformer. At the high end, we're seeing 180 megahertz minus 3db point, and then a second-order roll off. If we had not introduced the RLC filter between the amplifier and the converter, this would have been more like a 600 megahertz bandwidth, due to the transformer, which would have integrated quite a bit more noise, and degraded our SNR more so than we're going to see when we look at the FFT.
So with this test feature, which is built into the daughter board that you could acquire from the Intersil website, you can actually check the frequency response, and actually the distortion, right up to the ADC inputs.
But now let's move on to what we get in the FFT. So let's look now at the FFT that comes out of all this signal processing that we're performing here. This is available as a converter software version, that you download from the Intersil website. And what this is showing is that we're sampling at 500 megahertz or mega samples, which of course will fold all the data in to 250 megahertz. So this is showing the FFT output of the data capture card that we've been talking about.
So here we can see the key elements as our carrier, which is 105 megahertz. We are doing a Blackman-Harris four term windowing, since we're not doing synchronous sampling between the clock and the input, so we are using a windowing function. We're doing quite a number of samples. Our SNR full scale is 64.7. The converter itself specifies at 105 megahertz about 65.6dB, so we've lost just a little bit of performance there. We're seeing our dominant harmonics are the HD2 and HD3, as you would expect. They're at minus 83 and minus 82dBc, showing up here, and here. There's a little plus sign in there that's indicating that's the highest harmonic, which is the third harmonic.
We're getting about a 10.4 bit ENOB full scale, which is very close to the converter itself. So this summarizes all the characteristics that we've been doing to get up to this point, feeding 105 megahertz analog signal, at a very low power level, achieving a minus one dB full scale, and then getting the resulting spectrum coming through from both the amplifier and the ADC.
So now let's talk about how close we are to the ADC.
So in closing, there's clearly an awful lot going on here. We're taking a very high-speed signal and providing about 17dB gain, in this example, up to a 500 megahertz ADC. And what we're interested in is how much have we degraded the ADC performance from what the converter itself is capable of. We of course are trying to degrade this as little as possible, but zero degradation is impossible. In the solution we've been demonstrating here, the amplifier is only consuming about 115 milliwatts of power. We're getting an SNR degradation of about .9dB, which calculates out to a SNR coming into the converter that's about 5dB better. On the SFDR side, we're seeing about a 6 to 7dB degradation at 105 megahertz. The converter itself is typically in the 87 to 88dBc region at 105 megahertz input, and we're seeing about 83dB numbers. That indicates that we're coming in just a little bit better than the converter itself, so kind of in the minus 89 to 90dBc region.
So in summary, we've got a very low power interface, driving also a very low power converter, that gives us, we think, the most capable, high-performance digitizing channel available today.