- Generates 2 Regulated Voltages
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with Accurate VDDQ/2 Divider Reference
- Glitch-free Transitions During State Changes
- ACPI Compliant Sleep State Control
- Integrated VREF Buffer
- PWM Controller Drives Low Cost N-Channel MOSFETs
- 250kHz Constant Frequency Operation
- Tight Output Voltage Regulation
- Both Outputs: ±2% Over Temperature
- 5V or 3.3V Down Conversion
- Fully-Adjustable Outputs with Wide Voltage Range: Down to 0.8V supports DDR and DDR2 Specifications
- Simple Single-Loop Voltage-Mode PWM Control Design
- Fast PWM Converter Transient Response
- Over Current Protection on VTT and Under/Over-Voltage Monitoring of Both Outputs
- Integrated Thermal Shutdown Protection
- QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves PCB Efficiency, Thinner in Profile
- Pb-free available
The ISL6532B provides a complete ACPI compliant power solution for up to 4 DIMM dual channel DDR/DDR2 memory systems. Included are both a synchronous buck controller and integrated LDO to supply VDDQ with high current during S0/S1 states and standby current during S3 state. During Run mode, a fully integrated sink-source regulator generates an accurate (VDDQ/2) high current VTT voltage without the need for a negative supply. A buffered version of the VDDQ/2 reference is provided as VREF.
The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltagemode control with fast transient response. Both the switching regulator and integrated standby LDO provide a maximum static regulation tolerance of ±2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0.8V.
Switching the memory core output between the PWM regulator and the standby LDO during state transitions is accomplished smoothly via the internal ACPI control circuitry. The NCH signal provides synchronized switching of a backfeed blocking switch during the transitions eliminating the need to route 5V Dual to the memory supply.
An integrated soft-start feature brings VDDQ into regulation in a controlled manner when returning to S0/S1 state from S4/S5 or mechanical off states. During S0 the PGOOD signal indicates that all supplies are within spec and operational.
Each output is monitored for under and over-voltage events. Current limiting is included on the VTT and VDDQ standby regulators. Thermal shutdown is integrated.
- Single and Dual Channel DDR Memory Power Systems in ACPI compliant PCs
- Graphics cards - GPU and memory supplies
- ASIC power supplies
- Embedded processor and I/O supplies
- DSP supplies
ACPI Regulator/Controller for Dual Channel DDR Memory Systems
17 Nov 2014
|17 Nov 2014||358 KB|
|Five Easy Steps to Create a Multi-Load Power Solution|
30 Jan 2017
|30 Jan 2017||502 KB|