- Dual voltage monitoring
- V2Mon operates independent of VCC
- Watchdog timer with selectable timeout intervals
- Low VCC detection and RESET assertion
- Four standard RESET threshold voltages
- User programmable VTRIP threshold
- RESET signal valid to VCC=1V
- Low power CMOS
- 20µA max standby current, watchdog on
- 1µA standby current, watchdog OFF
- 64Kbits of EEPROM
- 64 byte page size
- Built-in inadvertent write protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512 bytes of EEPROM array with programmable Block Lock™ protection
- 400kHz 2-wire interface
- Slave addressing supports up to 4 devices on the same bus
- 2.7V to 5.5V power supply operation
- Available Packages
- 14-lead SOIC
- 14-lead TSSOP
The X40626 combines four popular functions, Power-on RESET Control, Watchdog Timer, Dual Supply Voltage Supervision, and Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.
Applying power to the device activates the power-on RESET circuit which holds RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable timeout interval, the device activates the RESET signal. The user selects the interval from three pRESET values. Once selected, the interval does not change, even after cycling the power.
The device's low VCC detection circuitry protects the user's system from low voltage conditions, RESETting the system when VCC falls below the set minimum VCC trip point. RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry standard Vtrip thresholds are available. However, Intersil's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.
The memory portion of the device is a CMOS Serial EEPROM array with Intersil's Block Lock™ Protection. The array is internally organized as 64 bytes per page. The device features an 2-wire interface and software protocol allowing operation on an I2C bus.
The device utilizes Intersil's proprietary Direct Write™ cell, providing a minimum endurance of 100,000 page write cycles and a minimum data retention of 100 years.
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