- Challenge-response based authentication scheme using 32-Bit challenge code and 8-Bit authentication code.
- Fast and flexible authentication process. Multi-pass authentication can be used to achieve the highest security level if necessary.
- 16x8 OTP ROM stores up to three sets of 32-Bit host-selectable secrets with additional programmable memory for storage of up to 48-Bits of ID code and/or pack information.
- FlexiHash+ engine uses two sets of 32-Bit secrets for authentication code generation.
- Non-unique mapping of the secret key to an 8-Bit authentication code maximizes hacking difficulty due to need for exhaustive key search (superior to SHA-1).
- Supports 1-cell Li-Ion/Li-Poly and 3-cell series NiMH battery packs (2.6V ~ 4.8V operation), or powered by the XSD bus.
- XSD single-wire host bus interface communicates with all 8250-compatible UART's or a single GPIO. Supports CRC on read data and transfer bit-rate up to 23kbps.
- True "Zero Power" Sleep mode - automatically entered after a bus inactivity time-out period
- 5 Ld SOT-23 or 8 Ld TDFN (2mm x 3mm) packages
- -20°C to +85°C operating temperature range
- Pb-free plus anneal available (RoHS compliant)
The ISL9206 is a highly cost-effective fixed-secret hash engine based on Intersil's second generation FlexiHash™ technology. The device authentication is achieved through a challenge-response scheme customized for low-cost applications, where cloning via eavesdropping without knowledge of the device's secret code is not economically viable. When used for its intended applications, the ISL9206 offers the same level of effectiveness as other significantly more expensive high-maintenance hash algorithm and authentication schemes.
The ISL9206 has a wide operating voltage range, and is suitable for direct powering from a 1-cell Li-Ion/Li-Poly or a 3-cell series NiMH battery pack. The ISL9206 can also be powered by the XSD bus when the bus pull-up voltage is 3.3V or higher. The device connects directly to the cell terminals of a battery pack, and includes on-chip voltage regulation circuit, POR, and a non-crystal based oscillator for bus timing reference.
Communication with the host is achieved through a singlewire XSD interface - a light-weight subset of Intersil's ISD bus interface. The XSD bus is compatible for use with serial ports offered by all 8250 compatible UART's or a single GPIO (general purpose input and output) pin of a microprocessor.
A clone prevention solution utilizing the ISL9206 offers safety and revenue protection at the lowest cost and power, and is suitable for protection against after-market replacement for a wide variety of low-cost applications.
- Battery Pack Authentication
- Printer Cartridges
- Add-on Accessories
- Other Non-Monetary Authentication Applications
|VS Range (V)||2.6 to 4.8||2.6 to 4.8||2.6 to 4.8|
|Supply Current (μA)||0.15 in Sleep Mode/110 in Run Mode||0.15 in Sleep Mode/38 in Run Mode||0.15 in Sleep Mode/38 in Run Mode|
|Data Bus||Single Wire||Single Wire||Single Wire|
|Data Bus Speed||23 kbps||23 kbps||5.78 kbps|
|AN1167: Implementing XSD Host Using a GPIO|
Implementing XSD Host Using a GPIO
13 Nov 2014
|13 Nov 2014||160 KB|
FlexiHash+ For Battery Authentication
17 Nov 2014
|17 Nov 2014||445 KB|
|TB363: Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)|
Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)
13 Jan 2015
|13 Jan 2015||29 KB|
|ISL9206EVAL1 User Guide|
ISL9206EVAL1 User Guide
04 Dec 2014
|04 Dec 2014||509 KB|
|Five Easy Steps to Create a Multi-Load Power Solution|
30 Jan 2017
|30 Jan 2017||502 KB|