Zynq UltraScale+ MPSoC

Power Rail Optimization

Xilinx’s Zynq UltraScale+ MPSoC product family addresses a diverse range of end applications & customers.

When scalable power delivery solutions are required, Intersil's suite of FPGA solutions provide the flexibility and cost efficiency to meet your design needs.

Learn more about Xilinx Zynq UltraScale+ devices »

Intersil has identified sixteen use cases based on your application's power supply consolidation needs and selected Xilinx Zynq UltraScale+ device:

  Optimized
for Cost
Optimized
for Power
Optimized for
Performance
Full Power
Management
ZU2 – ZU3 Use Case 1.1 Use Case 2.1 Use Case 3.1 Use Case 4.1
ZU4 – ZU5 Use Case 1.2 Use Case 2.2 Use Case 3.2 Use Case 4.2
ZU6 – ZU9 Use Case 1.3 Use Case 2.3 Use Case 3.3 Use Case 4.3
ZU11 – ZU19 Use Case 1.4 Use Case 2.4 Use Case 3.4 Use Case 4.4

 

Power Supply Consolidation Solutions

Select the design scenario that best meets the needs of your application to find custom power solutions and complete application schematic and BOM files:

Always On: Cost-Optimized Power Rail Consolidation

Rail Voltage Power SupplyRails
Rail 1 0.85/0.9V VCCINT, VCCINT_VCU, VCCBRAM, VCCINT_IO, VCC_PSINTLP, VCC_PSINTFP, VCC_PSINTFP_DDR
Rail 2* 1.8V* VCCAUX, VCCAUX_IO, VCCADC, VCC_PSAUX, VCC_PSDDR_PLL, VCC_PSADC
Rail 3* 1.2V* VMGTAVTT (GTH), VMGTYAVTT (GTY), VCC_PSPLL
Rail 4 1-1.5V VCCO_PSDDR, DDR_VDD2, DDR_VDDQ
Rail 5 1.8-3.3V VCCO_PSIO
Rail 6* 0.85/0.9V* VPS_MGTRAVCC
Rail 7* 1.8V* VMGTVCCAUX (GTH), VMGTYVCCAUX (GTY), VPS_MGTRAVTT
Rail 8* 0.9V* VMGTAVCC (GTH), VMGTYAVCC (GTY)
Rail 9 1.2-3.3V HDIO VCCO
Rail 10 1.0-1.8V HPIO VCCO

* Please see the Xilinx UltraScale Architecture PCB Design User Guide for additional rail specifications.

Key Features of Cost Optimized Solutions

Offers lowest device and power delivery solution cost

SW control of advanced Processing System (PS) power management schemes only

  • No access to low power (~mW) states

Simple power supply requirements – large number of rails grouped

  • Generally applicable to -1 & -2 speed grade devices

Use Case 1.1

  • For ZU2 – ZU3

High Load Rail:

Rail 1 = 6.15-7.75A

Recommended Parts

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Power Supply Reference Demo Board for the Xilinx Zynq Ultrascale+™ MPSoC (Use Case 1)

Power Supply Reference Demo Board for the Xilinx Zynq Ultrascale+™ MPSoC (Use Case 1)

The ISLUSPLUS-UC1DEMO1Z design provides a power supply reference solution for the Xilinx Zynq UltraScale+™ MPSoC. The power supply rail consolidation is based on the configuration for always on, optimized for cost (Use Case 1). The ISLUSPLUS-UC1DEMO1Z reference design is suitable for the Zynq UltraScale+ ZU2CG, ZU2EG(A), ZU3CG, and ZU3EG devices.

Learn More About ISLUSPLUS-UC1DEMO1Z »


Use Case 1.2

  • For ZU4 – ZU5

High Load Rail:

Rail 1 = 9.95-15.25A

Recommended Parts

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Use Case 1.3

  • For ZU6 – ZU9

High Load Rails:

Rail 1 = 18.25-23.95A
Rail 3 = 2.1A
Rail 8 = 2A

Recommended Parts

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Use Case 1.4

  • For ZU11 – ZU19

High Load Rails:

Rail 1 = 26.15-35.35A
Rail 2 = 1.54-2.04A
Rail 3 = 2.6-10.6A
Rail 8 = 2.5-7.5A

Recommended Parts

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Always On: Power and/or Efficiency-Optimized Power Rail Consolidation

Rail Voltage Power Supply Rails
Rail 1 0.72/0.85V VCCINT
Rail 2 0.85/0.9V VCC_PSINTFP, VCC_PSINTLP, VCC_PSINTFP_DDR, VCCINT_VCU, VCCINT_IO, VCCBRAM
Rail 3* 1.8V* VCC_PSAUX, VCCAUX, VCCAUX_IO, VCC_PSDDR_PLL, VCCADC, VCC_PSADC
Rail 4* 1.2V* VMGTAVTT (GTH), VMGTYAVTT (GTY), VCC_PSPLL
Rail 5 1.1-1.5V VCCO_PSDDR
Rail 6 1.8-3.3V VCCO_PSIO
Rail 7* 0.85V* VPS_MGTRAVCC
Rail 8* 1.8V* VMGTVCCAUX (GTH), VMGTYVCCAUX (GTY)
Rail 9* 0.9V* VMGTAVCC (GTH), VMGTYAVCC (GTY)
Rail 10 1.2-3.3V HDIO_VCCO
Rail 11 1-1.8V HPIO_VCCO

* Please see the Xilinx UltraScale Architecture PCB Design User Guide for additional rail specifications.

Key Features of Power Optimized Solutions

Targets lower Programmable Logic (PL) power & higher device efficiency (Perf/Watt)

SW control of advanced Processing System (PS) power management schemes only

  • No access to low power (~mW) states

One independent rail required for VCCINT (largest current rail)

  • Applicable to -1LI & -2LE devices where VCCINT=0.72V/programmable

Power Supply Reference Demo Board for the Xilinx Zynq Ultrascale+™ MPSoC (Use Case 2)

Power Supply Reference Demo Board for the Xilinx Zynq Ultrascale+™ MPSoC (Use Case 2)

The ISLUSPLUS-UC2DEMO1Z design provides a power supply reference solution for the Xilinx Zynq UltraScale+™ MPSoC. The power supply rail consolidation is based on the configuration for always on, optimized for power and/or efficiency (Use Case 2). The ISLUSPLUS-UC2DEMO1Z reference design is suitable for the Zynq Ultrascale+ ZU11EG, ZU15EG, ZU17EG, and ZU19EG devices.

Learn More About ISLUSPLUS-UC2DEMO1Z »


Use Case 2.1

  • For ZU2 – ZU3

High Load Rails:

Rail 1 = 3.2-4.2A
Rail 2 = 2.95-3.55A

Recommended Parts

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Use Case 2.2

  • For ZU4 – ZU5

High Load Rails:

Rail 1 = 7-8.7A
Rail 2 = 2.95-6.55A

Recommended Parts

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Use Case 2.3

  • For ZU6 – ZU9

High Load Rails:

Rail 1 = 15-20A
Rail 2 = 3.25-6.85A
Rail 4 = 2.1A
Rail 9 = 2A

Recommended Parts

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Use Case 2.4

  • For ZU11 – ZU19

High Load Rails:

Rail 1 = 22-31A
Rail 2 = 4.15-4.35A
Rail 3 = 1.54-2.04A
Rail 4 = 2.6-10.6A
Rail 9 = 2.5-7.5A

Recommended Parts

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Always On: PL Performance-Optimized Rail Consolidation

Rail Voltage Power Supply Rails
Rail 1 0.85/0.9V VCCINT, VCC_PSINTFP, VCC_PSINTLP, VCC_PSINTFP_DDR, VCCINT_VCU, VCCINT_IO, VCCBRAM
Rail 2* 1.8V* VCC_PSAUX, VCCAUX, VCCAUX_IO, VCC_PSDDR_PLL, VCCADC, VCC_PSADC
Rail 3* 1.2V* VMGTAVTT (GTH), VMGTYAVTT (GTY), VCC_PSPLL
Rail 4 1.1-1.5V VCCO_PSDDR
Rail 5 1.8-3.3V VCCO_PSIO
Rail 6* 1.8V* VMGTVCCAUX (GTH), VMGTYVCCAUX (GTY), VPS_MGTRAVTT
Rail 7* 0.9V* VMGTAVCC (GTH), VMGTYAVCC (GTY), VPS_MGTRAVCC
Rail 8 1.2-3.3V HDIO_VCCO
Rail 9 1-1.8V HPIO_VCCO

* Please see the Xilinx UltraScale Architecture PCB Design User Guide for additional rail specifications.

Key Features of Performance Optimized Solutions

Gives highest device performance but consumes more power

SW control of advanced Processing System (PS) power management schemes only

  • No access to low power (~mW) states

Simple power supply requirements – large number of rails grouped

  • Generally applicable to the -3E speed grade devices

Use Case 3.1

  • For ZU2 – ZU3

High Load Rail:

Rail 1 = 6.15-7.57A

Recommended Parts

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Use Case 3.2

  • For ZU4 – ZU5

High Load Rail:

Rail 1 = 9.95-15.25A

Recommended Parts

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Use Case 3.3

  • For ZU6 – ZU9

High Load Rails:

Rail 1 = 18.25-23.95A
Rail 3 = 2.1A
Rail 7 = 2.3A

Recommended Parts

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Use Case 3.4

  • For ZU11 – ZU19

High Load Rails:

Rail 1 = 26.15-35.35A
Rail 2 = 1.54-2.04A
Rail 3 = 2.6-10.6A
Rail 7 = 2.8-7.8A

Recommended Parts

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Full Power Domain Flexibility Consolidation

Rail Voltage Power Supply Rails
Rail 1 0.85V VCC_PSINTLP
Rail 2 1.8V VCC_PSAUX, VCC_PSADC
Rail 3* 1.2V* VCC_PSPLL
Rail 4 1.8-3.3V VCCO_PSIO
Rail 5 0.85/0.9V VCC_PSINTFP, VCC_PSINTFP_DDR
Rail 6* 1.8V* VCC_PSDDR_PLL
Rail 7 1.1-1.5V VCCO_PSDDR
Rail 8* 0.85V VCCINT_VCU, VCCINT, VCCINT_I, VCBRAM
Rail 9* 1.8V VCCAUX, VCCAUX_IO, VCCADC, DDR_VPP1
Rail 10* 0.85V* VPS_MGTRAVCC
Rail 11* 1.8V* VPS_MGTRAVTT
Rail 12* 1.2V VMGTAVTT (GTH), VMGTYAVTT (GTY)
Rail 13* 0.9V VMGTAVCC (GTH), VMGTYAVCC (GTY)
Rail 14* 1.8V VMGTVCCAUX (GTH), VMGTYVCCAUX (GTY)
Rail 16 1.2-3.3V HDIO_VCCO
Rail 17 1-1.8V HPIO_VCCO

* Please see the Xilinx UltraScale Architecture PCB Design User Guide for additional rail specifications.

Key Features of Full Power Management Solutions

Independent control of the different power domains for access to low power (~mW) states

  • e.g. battery powered app

Large number of independent rails

  • Applicable to all speed grades

Use Case 4.1

  • For ZU2 – ZU3

High Load Rails:

Rail 5 = 2.15-2.75A
Rail 8 = 3.6-4.6A

Recommended Parts

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Use Case 4.2

  • For ZU4 – ZU5

High Load Rails:

Rail 5 = 2.15-2.75A
Rail 8 = 7.4-12.1A

Recommended Parts

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Use Case 4.3

  • For ZU6 – ZU9

High Load Rails:

Rail 5 = 2.15-2.75A
Rail 8 = 15.7-20.8A
Rail 12 = 2.05A
Rail 13 = 2A

Recommended Parts

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Use Case 4.4

  • For ZU11 – ZU19

High Load Rails:

Rail 5 = 2.75A
Rail 8 = 23—32.2A
Rail 12 = 2.5-10.5A
Rail 13 = 2.5-7.5A

Recommended Parts

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Each of the Intersil designed solutions meet the Xilinx power requirements:

Supply Rails Load Step Slew Rate Voltage Limit
PL Core voltage (VCCINT) 25% 10A/us ±3%
VCCBRAM 40% 10A/us ±3%
VCCAUX/VCCAUX_IO 100% 10A/us ±3%
I/O Supplies 100% 10A/us ±5%
PS Core voltage (VCC_PSINT*P) 50% 10A/us ±5%
GTY/H/R 50% 10A/us ±3%

Take the guess work out of designing your power management stage with reference design solutions tailored for latest generation and legacy Xilinx FPGAs.

PowerCompass

The PowerCompass™ tool helps you design your power supply in minutes, giving you tools to find Intersil parts that match your requirements, set up multiple rails if needed, perform high-level system analysis and generate reference design files.

PowerCompass supports over 200 FPGAs, including built-in templates for Xilinx FPGA families. You can even save time by importing Xilinx Power Estimator output files to get system efficiency and power dissipation projections.

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