Device Information
 
 
X9470 Printer Friendly Version
 
RF Power Amplifier (PA) Bias Controller
 
Datasheets,
Related Docs
& Simulations
DescriptionKey
Features
Parametric
Data
Application
Diagrams
 
 
Ordering Information
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Part No. Design-In
Status
Temp. Package MSL Price
US $
PB Free
X9470V24I InActive Ind 24 Ld TSSOP 1 N/A      
The price listed is the manufacturer's suggested retail price for quantities of 1K units. However, prices in today's market are fluid and may change without notice.
MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020
SMD = Standard Microcircuit Drawing
 
  Description

The Intersil X9470 RF PA Bias Controller contains all of the necessary analog components to sense the PA drain current through an external sense resistor and automatically control the gate bias voltage of an LDMOS PA. The external sense resistor voltage is amplified by an instrumentation amplifier and the output of the amplifier along with an external reference voltage is fed to the inputs of a comparator. The comparator output indicates which direction the LDMOS gate bias voltage will move in the next calibration cycle. System calibration is accomplished by enabling the X9470 and providing a clock to the SCL pin. The LDMOS drain current can be maintained constant over temperature and aging changes by periodic calibration. The VOUT pin can be used to monitor the average power by tracking the drain current. Up to eight X9470 or additional Intersil Digital Potentiometers can be controlled via a twowire serial bus.

 
  Key Features
 
  • Programmable Bias Controller IC for Class A and AB LDMOS Power Amplifiers
  • Adaptive System on Chip Solution
  • Bias Current Calibration to better than ±4% using Reference Trim DCP
  • Automatic Bias Point Tracking and Calibration
    • IDQ Sensing and Tracking
    • Programmable Instrumentation Amplifier to Scale Wide Range of IDQ
    • Programmable Gate Bias Driver
    • All Programmable settings are Nonvolatile
    • All Settings Recalled at Power-up.
  • 28V Maximum VDD
  • 2 Wire Interface for Programming Bias Setting and Optimizing IDQ Set Point
  • Bias Level Comparator
  • Shutdown Control pin for PA Signal
  • Slave address to allow for multiple devices
  • 24-pin TSSOP Package
  • Applications: Cellular Base Stations (GSM, UMTS, CDMA, EDGE), TDD applications, Pointto- multipoint, and other RF power transmission systems
Related Documentation
 
Datasheet(s)   Datasheet(s):
 
  Parametric Data
26V (Typical) Instrumentation Anti-Dither (Drain Sense) AmplifierY
IDQ Sense and TrackingY
8-Bit (256-Tap) Gate Voltage Adjust OutputY
Gate Voltage Output BufferY
VREF InputY
Non-Volatile Storage of Gate Voltage SettingY
Input for Temperature Compensation CircuitsY
Optional Automatic/Periodic Control for Drain Current Sense to Gate Voltage AdjustmentY
Power On Recall CircuitsY
Bus Interface2-Wire
 
  Application Block Diagrams
 

 

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