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| 12-Bit, 500MSPS Single-Channel ADC, with LVDS/LVCMOS Outputs |
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| Ordering Information |
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 iBuy direct from Intersil
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 iBuy direct - out of stock
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 Request samples
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 Check distributor inventory
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Available in RoHS/Pb-Free
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Part No. |
Design-In
Status |
Temp. |
Package |
MSL |
Price
US $ |
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| KAD5512P-50Q72 |
Active |
Ind |
72 Ld QFN |
3 |
125.00 |
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| KDC5512-50EVALZ |
Active |
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Eval Board |
N/A |
Contact Us |
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| The price listed is the manufacturer's suggested retail price for quantities of 1K units. However, prices in today's market are fluid and may change without notice. |
| MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020 |
| SMD = Standard Microcircuit Drawing |
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 Description |
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The KAD5512P-50 is a low-power, high-performance, 12-bit, 500MSPS analog-to-digital converter designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process. The KAD5512P-50 is part of a pin-compatible portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging from 125MSPS to 500MSPS. The device utilizes two time-interleaved 12-bit, 250MSPS A/D cores to achieve the ultimate sample rate of 500MSPS.
A single 500MHz conversion clock is presented to the converter, and all interleave clocking is managed internally.
A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of matching characteristics (gain, offset, skew) between the two converter cores. These adjustments allow the user to minimize spurs associated with the interleaving process.
Digital output data is presented in selectable LVDS or CMOS formats. The KAD5512P-50 is available in a 72-contact QFN package with an exposed paddle. Performance is specified over the full industrial temperature range (-40°C to +85°C). |
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 Key Features |
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Programmable Gain, Offset and Skew control
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1.3GHz Analog Input Bandwidth
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60fs Clock Jitter
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Over-Range Indicator
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Selectable Clock Divider: ÷1 or ÷2
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Clock Phase Selection
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Nap and Sleep Modes
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Two’s Complement, Gray Code or Binary Data Format
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DDR LVDS-Compatible or LVCMOS Outputs
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Programmable Built-in Test Patterns
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Single-Supply 1.8V Operation
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Pb-Free (RoHS Compliant)
Key Specifications -
SNR = 65.9dBFS for fIN = 105MHz (-1dBFS)
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SFDR = 82.0dBc for fIN = 105MHz (-1dBFS)
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Total Power Consumption = 432mW
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| Related Documentation |
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 Application Note(s): |
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 Datasheet(s): |
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 Evaluation Board(s): |
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 Technical Homepage: |
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 Design Model(s): |
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 Parametric Data |
| | Resolution (Bits) | | 12 | | | Conv. Rate (MSPS) | | 500 | | | Channels | | 1 | | | SNR (dBFS) | | 65.9 | | | SFDR (dBc) | | 87.3 | | | Power (mW) | | 432 | | | Supply Voltage (V) | | Multi (1.8 Anlg, 1.8 Dig) | | | Input BW (MHz) | | 1300 | | | Input VIN (Range) (VP-P, differential) | | 1.45 | | | INL (max) (±LSB) | | 1.4 (typ) | | | DNL (max) (±LSB) | | 0.7 (typ) | |
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 Application Block Diagrams |
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| Applications |
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- Radar and Satellite Antenna Array Processing
- Broadband Communications
- High-Performance Data Acquisition
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| | KAD5512HP-12 | | 12-Bit, 125MSPS Single-Channel ADC with LVDS/LVCMOS Outputs | | | KAD5512HP-17 | | 12-Bit, 170MSPS Single-Channel ADC with LVDS/LVCMOS Outputs | | | KAD5512HP-21 | | 12-Bit, 210MSPS Single-Channel ADC with LVDS/LVCMOS Outputs | | | KAD5512HP-25 | | 12-Bit, 250MSPS Single-Channel ADC with LVDS/LVCMOS Outputs | | | KAD5512P-12 | | 12-Bit, 125MSPS Single-Channel ADC with LVDS/LVCMOS Outputs | | | KAD5512P-17 | | 12-Bit, 170MSPS Single-Channel ADC with LVDS/LVCMOS Outputs | | | KAD5512P-21 | | 12-Bit, 210MSPS Single-Channel ADC with LVDS/LVCMOS Outputs | | | KAD5512P-25 | | 12-Bit, 250MSPS Single-Channel ADC with LVDS/LVCMOS Outputs | |
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