Device Information
 
 
ISL6548A Printer Friendly Version
 
ACPI Regulator/Controller for Dual Channel DDR Memory Systems
 
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DescriptionKey
Features
Parametric
Data
Application
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Ordering Information
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 Check distributor inventory Green/Pb(Lead free) Device  Available in RoHS/Pb-Free  
Part No. Design-In
Status
Temp. Package MSL Price
US $
PB Free
ISL6548A-6506EVAL1Z Active   Eval Board N/A Contact Us PB Free Disti-Buy  
ISL6548ACRZA Active Comm 28 Ld QFN 3 3.17 PB Free Buy Direct Disti-Buy Sample
ISL6548ACRZA-T Active Comm 28 Ld QFN T+R 3 3.17 PB Free Disti-Buy  
ISL6548ACRZ InActive Comm 28 Ld QFN 3 N/A PB Free    
ISL6548ACRZ-T InActive Comm 28 Ld QFN T+R 3 N/A PB Free    
The price listed is the manufacturer's suggested retail price for quantities of 1K units. However, prices in today's market are fluid and may change without notice.
MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020
SMD = Standard Microcircuit Drawing
 
  Description

The ISL6548A provides a complete ACPI compliant power solution for up to 4 DIMM dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller to supply VDDQ during S0/S1 and S3 states. During S0/S1 state, a fully integrated sink-source regulator generates an accurate (VDDQ/2) high current VTT voltage without the need for a negative supply. A second PWM controller, which requires external MOSFET drivers, is available for regulation of the GMCH Core voltage. A sink/source LDO controller is also integrated for the CPU/GMCH VTT termination voltage regulation. Another LDO is available for the ICH7 voltage.

The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltagemode control with fast transient response. The switching regulator provides a maximum static regulation tolerance of ±2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0.8V.

An integrated soft-start feature brings all outputs into regulation in a controlled manner when returning to S0/S1 state from any sleep state. During S0 the VIDPGD signal indicates that the GMCH and CPU VTT termination voltage is within spec and operational.

All outputs, except VICH7, have undervoltage protection. The switching regulator also has overvoltage and overcurrent protection. Thermal shutdown is integrated.

 
  Key Features
 
  • Generates 5 Regulated Voltages
    • Synchronous Buck PWM Controller for DDR VDDQ
    • 3A Integrated Sink/Source Linear Regulator with Accurate VDDQ/2 Divider Reference for DDR VTT
    • PWM Regulator for GMCH Core
    • Sink/Source LDO Regulator for CPU/GMCH VTT Termination
    • LDO Regulator for ICH7
  • ACPI compliant sleep state control
  • Glitch-free Transitions During State Changes
  • VDDQ PWM Controller Drives Low Cost N-Channel MOSFETs
  • 250kHz Constant Frequency Operation
    • Both PWM controllers are Phase Shifted 180°
  • Tight Output Voltage Regulation
    • All Outputs: ±2% Over Temperature
  • Fully-Adjustable Outputs with Wide Voltage Range: Down to 0.8V supports DDR and DDR2 Specifications
  • Simple Single-Loop Voltage-Mode PWM Control Design
  • Fast PWM Converter Transient Response
  • Under and Overvoltage Monitoring
  • OCP on the VDDQ Switching Regulator
  • Integrated Thermal Shutdown Protection
  • Pb-Free Plus Anneal Available (RoHS Compliant)
Related Documentation
 
Application Note(s)   Application Note(s):
 
Datasheet(s)   Datasheet(s):
 
 
  Parametric Data
VIN (min) (V)5.5
VIN (max) (V)4.5
VOUT1 (min) (V).8
VOUT1 (max) (V)VIN
VOUT2 (V)50% of VOUT1
VOUT3 (V)Adjustable down to 0.8V
VOUT4 (V)Adjustable down to 0.8V
VOUT5 (V)Adjustable down to 0.8V
 
  Application Block Diagrams
 
 
 
Applications
 
  • Single and Dual Channel DDR Memory Power Systems in ACPI compliant PCs
  • Graphics cards - GPU and memory supplies
  • ASIC power supplies
  • Embedded processor and I/O supplies
  • DSP supplies
 
  Related DevicesParametric Table   Parametric Table
 
 ISL6537A ACPI Regulator/Controller for Dual Channel DDR Memory Systems 

 

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