ISL6537 ACPI Regulator/Controller for Dual Channel DDR Memory Systems

ISL6537

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ACPI Regulator/Controller for Dual Channel DDR Memory Systems

Datasheets,
Related Docs
& Simulations

Ordering Information

iBuy direct from Intersil	iBuy direct - out of stock	Request samples
Check distributor inventory	Available in RoHS/Pb-Free

Part No.

Design-In
Status

Temp.

Package

MSL

Price
US $

ISL6537CRZ

Active

Comm

28 Ld QFN

2.87

ISL6537CRZ-T

Active

Comm

28 Ld QFN T+R

2.87

ISL6537_6506EVAL1

Active

Eval Board

N/A

ISL6537CR

InActive

Comm

28 Ld QFN

N/A

ISL6537CR-T

InActive

Comm

28 Ld QFN T+R

N/A

The price listed is the manufacturer's suggested retail price for quantities of 1K units. However, prices in today's market are fluid and may change without notice.

MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020

SMD = Standard Microcircuit Drawing

Description

The ISL6537 provides a complete ACPI compliant power solution for up to 4 DIMM dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller to supply V_DDQ during S0/S1 and S3 states. During S0/S1 state, a fully integrated sink-source regulator generates an accurate (V_DDQ/2) high current V_TT voltage without the need for a negative supply. A buffered version of the V_DDQ/2 reference is provided as V_REF. Two LDO controllers are also integrated for the GMCH core voltage regulation and for the GMCH and CPU V_TT termination voltage regulation.

The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltage-mode control with fast transient response. The switching regulator provides a maximum static regulation tolerance of ±2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0.8V.

An integrated soft-start feature brings all outputs into regulation in a controlled manner when returning to S0/S1 state from any sleep state. During S0 the VIDPGD signal indicates that the GMCH and CPU V_TT termination voltage is within spec and operational.

Each output is monitored for undervoltage events. The switching regulator also has overvoltage and overcurrent protection. Thermal shutdown is integrated.

Key Features

Generates 4 Regulated Voltages
- Synchronous Buck PWM Controller for DDR V_DDQ
- 3A Integrated Sink/Source Linear Regulator with Accurate V_DDQ/2 Divider Reference for DDR V_TT
- LDO Regulator for GMCH Core
- LDO Regulator for CPU/GMCH V_TT Termination
ACPI Compliant Sleep State Control
Glitch-free Transitions During State Changes
Integrated V_REF Buffer
PWM Controller Drives Low Cost N-Channel MOSFETs
250kHz Constant Frequency Operation
Tight Output Voltage Regulation
- All Outputs: ±2% Over Temperature
Fully-Adjustable Outputs with Wide Voltage Range: Down to 0.8V supports DDR and DDR2 Specifications
Simple Single-Loop Voltage-Mode PWM Control Design
Fast PWM Converter Transient Response
Under and Overvoltage Monitoring on All Outputs
OCP on the Switching Regulator
Integrated Thermal Shutdown Protection
Pb-Free Plus Anneal Available (RoHS Compliant)

Related Documentation

Application Note(s):
Embedded ACPI Compliant DDR Power Generation Using the ISL6537 and ISL6506

Datasheet(s):
ACPI Regulator/Controller for Dual Channel DDR Memory Systems

Parametric Data


V_IN (min) (V)		4.5

V_IN (max) (V)		5.5

V_OUT1 (min) (V)		.8

V_OUT1 (max) (V)		V_IN

V_OUT2 (V)		50% of V_OUT1

V_OUT3 (V)		Adjustable down to 0.8V

V_OUT4 (V)		Adjustable down to 0.8V

I_OUT1 (A)		25

Application Block Diagrams

Applications

Single and Dual Channel DDR Memory Power Systems in ACPI Compliant PCs
Graphics Cards - GPU and Memory Supplies
ASIC Power Supplies
Embedded Processor and I/O Supplies
DSP Supplies

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