| |
|
| |
| Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination |
| |
|
| |
| |
| Ordering Information |
|
 |
 |
|
 iBuy direct from Intersil
|
 iBuy direct - out of stock
|
 Request samples
|
 Check distributor inventory
|
Available in RoHS/Pb-Free
|
|
|
|
|
|
|
Part No. |
Design-In
Status |
Temp. |
Package |
MSL |
Price
US $ |
|
|
|
|
|
|
| ISL6531CB |
InActive |
Comm |
24 Ld SOIC |
1 |
N/A |
| |
|
|
|
|
| ISL6531CB-T |
InActive |
Comm |
24 Ld SOIC T+R |
1 |
N/A |
| |
|
|
|
|
| ISL6531CBZ |
InActive |
Comm |
24 Ld SOIC |
3 |
N/A |
 |
|
|
|
|
|
| ISL6531CBZ-T |
InActive |
Comm |
24 Ld SOIC T+R |
3 |
N/A |
|
|
|
|
|
|
| ISL6531CR |
InActive |
Comm |
32 Ld QFN |
1 |
N/A |
| |
|
|
|
|
| ISL6531CR-T |
InActive |
Comm |
32 Ld QFN T+R |
1 |
N/A |
| |
|
|
|
|
| ISL6531CRZ |
InActive |
Comm |
32 Ld QFN |
3 |
N/A |
|
|
|
|
|
|
| ISL6531CRZ-T |
InActive |
Comm |
32 Ld QFN T+R |
3 |
N/A |
|
|
|
|
|
|
| ISL6531EVAL1 |
InActive |
|
Eval Board |
N/A |
N/A |
| |
|
|
|
|
| ISL6531EVAL2 |
InActive |
|
Eval Board |
N/A |
N/A |
| |
|
|
|
|
| The price listed is the manufacturer's suggested retail price for quantities of 1K units. However, prices in today's market are fluid and may change without notice. |
| MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020 |
| SMD = Standard Microcircuit Drawing |
|
| |
 Description |
|
|
The ISL6531 provides complete control and protection for dual DC-DC converters optimized for high-performance DDRAM memory applications. It is designed to drive low cost N-channel MOSFETs in synchronous-rectified buck topology to efficiently generate 2.5V VDDQ for powering DDRAM memory, VREF for DDRAM differential signalling, and VTT for signal termination. The ISL6531 integrates all of the control, output adjustment, monitoring and protection functions into a single package.
The VDDQ output of the converter is maintained at 2.5V through an integrated precision voltage reference. The VREF output is precisely regulated to 1/2 the memory power supply, with a maximum tolerance of ±1% over temperature and line voltage variations. VTT accurately tracks VREF. During V2_SD sleep mode, the VTT output is maintained by a low power window regulator.
The ISL6531 provides simple, single feedback loop, voltagemode control with fast transient response for the VDDQ regulator. The VTT regulator features internal compensation that eases the design. It includes two phase-locked 300kHz triangle-wave oscillators which are displaced 90o to minimize interference between the two PWM regulators. The regulators feature error amplifiers with a 15MHz gainbandwidth product and 6V/µs slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty ratio ranges from 0% to 100%.
The ISL6531 protects against overcurrent conditions by inhibiting PWM operation. The ISL6531 monitors the current in the VDDQ regulator by using the rDS(ON) of the upper MOSFET which eliminates the need for a current sensing resistor. |
| |
 Key Features |
|
|
| |
-
Provides VDDQ, VREF, and VTT voltages for one- and twochannel DDRAM memory systems
-
Excellent voltage regulation
-
VDDQ = 2.5V ±2% over full operating range
-
VREF = 1/2 · VDDQ ±1% over full operating range
-
VTT = VREF ±30mV
-
Supports 'S3' sleep mode
-
VTT is held at 1/2 · VDDQ via a low power window regulator to minimize wake-up time
-
Fast transient response
-
Full 0% to 100% duty ratio
-
Operates from +5V Input
-
VTT regulator internally compensated
-
Overcurrent fault monitor on VDD
-
Does not require extra current sensing element
-
Uses MOSFET's rDS(ON)
-
Drives inexpensive N-Channel MOSFETs
-
Small converter size
-
300kHz fixed frequency oscillator
-
24 Lead, SOIC or 32 Lead, 5mm×5mm QFN
-
Pb-Free Plus Anneal Available (RoHS Compliant)
|
| Related Documentation |
|
|
| |
 Datasheet(s): |
| | |
 Evaluation Board(s): |
| | | |
| |
 Parametric Data |
| | VIN (min) (V) | | 5 | | | VIN (max) (V) | | 5 | | | VOUT (min) (V) | | .8 | | | VOUT (max) (V) | | 5 | | | IOUT (max) (A) | | 20 | | | Switching Freq. (kHz) | | 300 | |
|
| |
 Application Block Diagrams |
|
| |
|
| |
| |
| Applications |
|
| |
- VDDQ, VTT, and VREF regulation for DDRAM memory systems
- Main memory in AMD® Athlon™ and K8™, Pentium® III, Pentium IV, Transmeta, PowerPC™, AlphaPC™, and UltraSparc® based computer systems
- High-power tracking DC-DC regulators
|
