Device Information
 
 
HSP43220 Printer Friendly Version
 
Decimating Digital Filter
 
Datasheets,
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& Simulations
DescriptionKey
Features
Parametric
Data
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Ordering Information
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Part No. Design-In
Status
Temp. Package MSL Price
US $
PB Free
HSP43220JC-25 Active Comm 84 Ld PLCC 4 120.17   Disti-Buy  
HSP43220JC-25Z Active Comm 84 Ld PLCC 4 92.20 PB Free Disti-Buy Sample
HSP43220JC-33 Active Comm 84 Ld PLCC 4 142.24   Disti-Buy  
HSP43220JC-33Z Active Comm 84 Ld PLCC 4 104.59 PB Free Disti-Buy Sample
HSP43881JC-25 InActive -   4 N/A      
The price listed is the manufacturer's suggested retail price for quantities of 1K units. However, prices in today's market are fluid and may change without notice.
MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020
SMD = Standard Microcircuit Drawing
 
  Description

The HSP43220 Decimating Digital Filter is a linear phase low pass decimation filter which is optimized for filtering narrow band signals in a broad spectrum of a signal processing applications. The HSP43220 offers a single chip solution to signal processing applications which have historically required several boards of ICs. This reduction in component count results in faster development times as well as reduction of hardware costs.

The HSP43220 is implemented as a two stage filter structure. As seen in the block diagram, the first stage is a high order decimation filter (HDF) which utilizes an efficient sample rate reduction technique to obtain decimation up to 1024 through a coarse low-pass filtering process. The HDF provides up to 96dB aliasing rejection in the signal pass band. The second stage consists of a finite impulse response (FIR) decimation filter structured as a transversal FIR filter with up to 512 symmetric taps which can implement filters with sharp transition regions. The FIR can perform further decimation by up to 16 if required while preserving the 96dB aliasing attenuation obtained by the HDF. The combined total decimation capability is 16,384.

The HSP43220 accepts 16-bit parallel data in 2's complement format at sampling rates up to 33 MSPS. It provides a 16-bit microprocessor compatible interface to simplify the task of programming and three-state outputs to allow the connection of several ICs to a common bus. The HSP43220 also provides the capability to bypass either the HDF or the FIR for additional flexibility.

 
  Key Features
 
  • Single Chip Narrow Band Filter with up to 96dB Attenuation
  • DC to 33MHz Clock Rate
  • 16-Bit 2's Complement Input
  • 20-Bit Coefficients in FIR
  • 24-Bit Extended Precision Output
  • Programmable Decimation up to a Maximum of 16,384
  • Standard 16-Bit Microprocessor Interface
  • Filter Design Software Available DECIMATE™
  • Up to 512 Taps
Related Documentation
 
Application Note(s)   Application Note(s):
 
Datasheet(s)   Datasheet(s):
 
Technical Brief(s)   Technical Brief(s):
 
Evaluation Board(s)   Evaluation Board(s):
 
Technical Homepage   Technical Homepage:
 
   Other:
 
  Parametric Data
SubtypeCIC FIR
Max Attenuation (dB)96
Compute Rate (Taps/sec)66
Filter TapsUp to 512
Data (Bits)16
Coefficient (Bits)20
Rate Change (Decimation or Interpolation)Up to 16,384
Control/μP Interface16-Bit Data
 
 
Applications
 
  • Very Narrow Band Filters
  • Zoom Spectral Analysis
  • Channelized Receivers
  • Large Sample Rate Converter
 
  Related DevicesParametric Table   Parametric Table
 
 HSP43124 Serial I/O Filter 
 HSP43168 Dual FIR Filter 
 HSP43216 Halfband Filter 

 

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