Device Information
 
 
HSP43168 Printer Friendly Version
 
Dual FIR Filter
 
Datasheets,
Related Docs
& Simulations
DescriptionKey
Features
Parametric
Data
Related
Devices
 
 
Ordering Information
 iBuy direct from Intersil  iBuy direct - out of stock  Request samples
 Check distributor inventory Green/Pb(Lead free) Device  Available in RoHS/Pb-Free  
Part No. Design-In
Status
Temp. Package MSL Price
US $
PB Free
HSP43168JC-33 Active Comm 84 Ld PLCC 4 57.93   Disti-Buy  
HSP43168JC-33Z Active Comm 84 Ld PLCC 4 46.47 PB Free Disti-Buy  
HSP43168VC-45 Active Comm 100 Ld MQFP 4 79.49   Disti-Buy  
HSP43168VC-45Z Active Comm 100 Ld MQFP 3 58.45 PB Free Disti-Buy  
HSP43168JI-40 InActive Ind 84 Ld PLCC 4 N/A      
HSP43168VC-33 InActive Comm 100 Ld MQFP 4 N/A      
HSP43168VC-40 InActive Comm 100 Ld MQFP 4 N/A      
The price listed is the manufacturer's suggested retail price for quantities of 1K units. However, prices in today's market are fluid and may change without notice.
MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020
SMD = Standard Microcircuit Drawing
 
  Description

The HSP43168 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR cells each fed by a separate coefficient bank and one of two separate inputs. The outputs of the FIR cells are either summed or multiplexed by the MUX/Adder. The compute power in the FIR Cells can be configured to provide quadrature filtering, complex filtering, 2-D convolution, 1-D/2-D correlations, and interpolating/decimating filters.

The FIR cells take advantage of symmetry in FIR coefficients by pre-adding data samples prior to multiplication. This allows an 8-tap FIR to be implemented using only 4 multipliers per filter cell. These cells can be configured as either a single 16-tap FIR filter or dual 8-tap FIR filters. Asymmetric filtering is also supported.

Decimation of up to 16 is provided to boost the effective number of filter taps from 2 to 16 times. Further, the Decimation Registers provide the delay necessary for fractional data conversion and 2-D filtering with kernels to 16x16.

The flexibility of the Dual is further enhanced by 32 sets of user programmable coefficients. Coefficient selection may be changed asynchronously from clock to clock. The ability to toggle between coefficient sets further simplifies applications such as polyphase or adaptive filtering. The HSP43168 is a low power fully static design implemented in an advanced CMOS process. The configuration of the device is controlled through a standard microprocessor interface.

 
  Key Features
 
  • Two Independent 8-Tap FIR Filters Configurable as a Single 16-Tap FIR
  • 10-Bit Data and Coefficients
  • On-Board Storage for 32 Programmable Coefficient Sets
  • Up To: 256 FIR Taps, 16x16 2-D Kernels, or 10x19-Bit Data and Coefficients
  • Programmable Decimation to 16
  • Programmable Rounding on Output
  • Standard Microprocessor Interface
  • Pb-Free Plus Anneal Available (RoHS Compliant)
Related Documentation
 
Application Note(s)   Application Note(s):
 
Datasheet(s)   Datasheet(s):
 
Technical Brief(s)   Technical Brief(s):
 
Evaluation Board(s)   Evaluation Board(s):
 
Technical Homepage   Technical Homepage:
 
   Other:
 
  Parametric Data
SubtypeFIR
Max Attenuation (dB)60
Compute Rate (Taps/sec)720
Filter Taps-240
Data (Bits)10
Coefficient (Bits)10
Rate Change (Decimation or Interpolation)-15
Control/μP Interface10-Bit Data 9-Bit Address
 
 
Applications
 
  • Quadrature, Complex Filtering
  • Image Processing
  • Polyphase Filtering
  • Adaptive Filtering
 
  Related DevicesParametric Table   Parametric Table
 
 HSP43124 Serial I/O Filter 
 HSP43216 Halfband Filter 
 HSP43220 Decimating Digital Filter 

 

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