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| Serial I/O Filter |
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| Ordering Information |
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iBuy direct from Intersil
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iBuy direct - out of stock
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Request samples
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Check distributor inventory
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Available in RoHS/Pb-Free
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Part No. |
Design-In Status |
Temp. |
Package |
MSL |
Price US $ |
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 | HSP43124SC-45 |
Active |
Comm |
28 Ld SOIC |
1 |
38.82 |
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 | HSP43124SC-45Z |
Active |
Comm |
28 Ld SOIC |
3 |
29.72 |
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 | HSP43124SI-40 |
InActive |
Ind |
28 Ld SOIC |
1 |
N/A |
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| The price listed is the manufacturer's suggested retail price for quantities of 1K units. However, prices in today's market are fluid and may change without notice. |
| MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020 |
| SMD = Standard Microcircuit Drawing |
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Description |
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The Serial I/O Filter is a high performance filter engine that is ideal for off loading the burden of filter processing from a DSP microprocessor. It supports a variety of multistage filter configurations based on a user programmable filter and fixed coefficient halfband filters. These configurations include a programmable FIR filter of up to 256 taps, a cascade of from one to five halfband filters, or a cascade of halfband filters followed by a programmable FIR. The half band filters each decimate by a factor of two, and the FIR filter decimates from one to eight. When all six filters are selected, a maximum decimation of 256 is provided.
For digital tuning applications, a separate multiplier is provided which allows the incoming data stream to be multiplied, or mixed, by a user supplied mix factor. A two pin interface is provided for serially loading the mix factor from an external source or selecting the mix factor from an on-board ROM. The on-board ROM contains samples of a sinusoid capable of spectrally shifting the input data by one quarter of the sample rate, FS/4. This allows the chip to function as a digital down converter when the filter stages are configured as a low-pass filter.
The serial interface for 3- input and output data is compatible with the serial ports of common DSP microprocessors. Coefficients and configuration data are loaded over a bidirectional eight bit interface. |
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Key Features |
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45MHz Clock Rate
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256 Tap Programmable FIR Filter
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24-Bit Data, 32-Bit Coefficients
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Cascade of up to 5 Half Band Filters
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Decimation from 1 to 256
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Two Pin Interface for Down Conversion by FS/4
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Multiplier for Mixing or Scaling Input with an External Source
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Serial I/O Compatible with Most DSP Microprocessors
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Pb-Free Plus Anneal Available (RoHS Compliant)
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| Related Documentation |
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Technical Homepage: |
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Parametric Data |
 | | Subtype |  | HB FIR |  | | Max Attenuation (dB) |  | 140 |  | | Compute Rate (Taps/sec) |  | 90 |  | | Filter Taps |  | Up to 256 (FIR) |  | | Data (Bits) |  | 24 |  | | Coefficient (Bits) |  | 32 |  | | Rate Change (Decimation or Interpolation) |  | 1 to 256 |  | | Control/μP Interface |  | 8-Bit Data 3-Bit Address WR RD |  |
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| Applications |
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- Low Cost FIR Filter
- Filter Co-Processor
- Digital Tuner
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