Device Information
 
 
HSP43124 Printer Friendly Version
 
Serial I/O Filter
 
Datasheets,
Related Docs
& Simulations
DescriptionKey
Features
Parametric
Data
Related
Devices
 
 
Ordering Information
 iBuy direct from Intersil  iBuy direct - out of stock  Request samples
 Check distributor inventory Green/Pb(Lead free) Device  Available in RoHS/Pb-Free  
Part No. Design-In
Status
Temp. Package MSL Price
US $
PB Free
HSP43124SC-45 Active Comm 28 Ld SOIC 1 38.82   Disti-Buy  
HSP43124SC-45Z Active Comm 28 Ld SOIC 3 29.72 PB Free Disti-Buy Sample
HSP43124SI-40 InActive Ind 28 Ld SOIC 1 N/A      
The price listed is the manufacturer's suggested retail price for quantities of 1K units. However, prices in today's market are fluid and may change without notice.
MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020
SMD = Standard Microcircuit Drawing
 
  Description

The Serial I/O Filter is a high performance filter engine that is ideal for off loading the burden of filter processing from a DSP microprocessor. It supports a variety of multistage filter configurations based on a user programmable filter and fixed coefficient halfband filters. These configurations include a programmable FIR filter of up to 256 taps, a cascade of from one to five halfband filters, or a cascade of halfband filters followed by a programmable FIR. The half band filters each decimate by a factor of two, and the FIR filter decimates from one to eight. When all six filters are selected, a maximum decimation of 256 is provided.

For digital tuning applications, a separate multiplier is provided which allows the incoming data stream to be multiplied, or mixed, by a user supplied mix factor. A two pin interface is provided for serially loading the mix factor from an external source or selecting the mix factor from an on-board ROM. The on-board ROM contains samples of a sinusoid capable of spectrally shifting the input data by one quarter of the sample rate, FS/4. This allows the chip to function as a digital down converter when the filter stages are configured as a low-pass filter.

The serial interface for 3- input and output data is compatible with the serial ports of common DSP microprocessors. Coefficients and configuration data are loaded over a bidirectional eight bit interface.

 
  Key Features
 
  • 45MHz Clock Rate
  • 256 Tap Programmable FIR Filter
  • 24-Bit Data, 32-Bit Coefficients
  • Cascade of up to 5 Half Band Filters
  • Decimation from 1 to 256
  • Two Pin Interface for Down Conversion by FS/4
  • Multiplier for Mixing or Scaling Input with an External Source
  • Serial I/O Compatible with Most DSP Microprocessors
  • Pb-Free Plus Anneal Available (RoHS Compliant)
Related Documentation
 
Application Note(s)   Application Note(s):
 
Datasheet(s)   Datasheet(s):
 
Evaluation Board(s)   Evaluation Board(s):
 
Technical Homepage   Technical Homepage:
 
   Other:
 
  Parametric Data
SubtypeHB FIR
Max Attenuation (dB)140
Compute Rate (Taps/sec)90
Filter TapsUp to 256 (FIR)
Data (Bits)24
Coefficient (Bits)32
Rate Change (Decimation or Interpolation)1 to 256
Control/μP Interface8-Bit Data 3-Bit Address WR RD
 
 
Applications
 
  • Low Cost FIR Filter
  • Filter Co-Processor
  • Digital Tuner
 
  Related DevicesParametric Table   Parametric Table
 
 HSP43168 Dual FIR Filter 
 HSP43216 Halfband Filter 
 HSP43220 Decimating Digital Filter 

 

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