Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ)
Dose Rate Survivability: >1 x 1012 RAD (Si)/s
Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
Cosmic Ray Upset Immunity < 2 x 10-9 Errors/Bit-Day (Typ)
Latch-Up Free Under Any Conditions
Military Temperature Range: -55oC to +125oC
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
Input Logic Levels
VIL = 30% of VCC Max
VIH = 70% of VCC Min
Input Current Levels Ii ≤ 5ľA at VOL, VOH
Description
The Intersil HCS109MS is a Radiation Hardened Dual JK Flip Flop with set and reset. The flip flop changes state with the positive transition of the clock (CP1 or CP2).
The HCS109MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS109MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).
The price listed is the manufacturer's suggested retail price for quantities of 1K units. However, prices in today's market are fluid and may change without notice.
MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020
SMD/VID = Standard Microcircuit Drawing/Vendor Item Drawing