The EL4584 is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS compatible Pixel Clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to it.

The reference signal is a horizontal sync signal, TTL/CMOS format, which can be easily derived from an analog composite video signal with the EL4583 Sync Separator. An input signal to "coast" is provided for applications were periodic disturbances are present in the reference video timing such as VTR head switching. The Lock detector output indicates correct lock.

The divider ratio is four ratios for NTSC and four similar ratios for the PAL video timing standards, by external selection of three control pins. These four ratios have been selected for common video applications including 4F_SC, 3F_SC, 13.5MHz (CCIR 601 format) and square picture elements used in some workstation graphics. To generate 8F_SC, 6F_SC, 27MHz (CCIR 601 format) etc. use the EL4585, which includes an additional divide-by-two stage.

For applications where these frequencies are inappropriate or for general purpose PLL applications the internal divider can be bypassed and an external divider chain used.

• 36MHz, general purpose PLL
• 4F_SC based timing (use the EL4585 for 8F_SC)
• Compatible with EL4583 sync separator
• VCXO, Xtal, or LC tank oscillator
• < 2ns jitter (VCXO)
• User controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed TV scan rate clock divisors
• Selectable external divide for custom ratios
• Single 5V, low current operation
• Pb-Free available (RoHS compliant)

• Pixel clock regeneration
• Video compression engine (MPEG) clock generator
• Video capture or digitization
• PIP (Picture in Picture) timing generator
• Text or graphics overlay timing