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| CMOS Dual J-K Master-Slave Flip-Flop |
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| Ordering Information |
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 iBuy direct from Intersil
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 iBuy direct - out of stock
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 Request samples
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 Check distributor inventory
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Available in RoHS/Pb-Free
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Part No. |
Design-In
Status |
Temp. |
Package |
MSL |
SMD/VID |
Price
US $ |
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| CD4027BKMSR |
Active |
Mil |
16 Ld FlatPack |
N/A |
5962R9662901VXC |
Contact Us |
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| The price listed is the manufacturer's suggested retail price for quantities of 1K units. However, prices in today's market are fluid and may change without notice. |
| MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020 |
| SMD/VID = Standard Microcircuit Drawing/Vendor Item Drawing |
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 Description |
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CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the Intersil CD4013B dual D type flip-flop.
The CD4027BMS is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip- flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input.
The CD4027BMS is supplied in these 16-lead outline packages:
Braze Seal DIP H4T
Frit Seal DIP H1E
Ceramic Flatpack H6W
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 Key Features |
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High Voltage Type (20V Rating)
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Set - Reset Capability
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Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either "High" or "Low"
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Medium Speed Operation - 16MHz (typ.) Clock Toggle Rate at 10V
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Standardized Symmetrical Output Characteristics
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100% Tested For Quiescent Current at 20V
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Maximum Input Current of 1ľA at 18V Over Full Package-Temperature Range;
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Noise Margin (Over Full Package Temperature Range):
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1V at VDD = 5V
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2V at VDD = 10V
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2.5V at VDD = 15V
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5V, 10V and 15V Parametric Ratings
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Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
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| Related Documentation |
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 Application Note(s): |
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 Datasheet(s): |
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 SMD Datasheet(s): |
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 Technical Homepage: |
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 Parametric Data |
| | DSCC SMD | | 5962-96629 | | | Class | | V | | | High Dose Rate (HDR) rad(Si) | | 100 | | | Low Dose Rate (ELDRS) | | ELDRS free | | | SEL MeV/mg/cm2 | | 75 | |
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| Applications |
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- Registers, Counters, Control Circuits
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| | ACS74MS | | CMOS Dual D Type Flip Flop with Set and Reset, Advanced Logic | | | ACTS74MS | | CMOS Dual D Type Flip Flop with Set and Reset, Advanced Logic | | | HCS109MS | | CMOS Dual JK Flip Flop | | | HCTS74MS | | CMOS Dual-D Flip-Flop with Set and Reset | |
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