The Intersil ACTS161MS is a Radiation Hardened 4-Bit Binary Synchronous Counter, featuring asynchronous reset and load ahead carry logic. The MR is an active low master reset. SPE is an active low Synchronous Parallel Enable which disables counting and allows data at the preset inputs (P0 - P3) to load the counter. CP is the positive edge clock. TC is the terminal count or carry output. Both TE and PE must be high for counting to occur, but are irrelevant to loading. TE low will keep TC low.

The ACTS161MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic family.

The ACTS161MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix).

• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96716 and Intersil's QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10^-10 Errors/Bit/Day (Typ)
• SEU LET Threshold >100 MEV-cm²/mg
• Dose Rate Upset >10¹¹ RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability >10¹² RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range -55^oC to +125^oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range 4.5V to 5.5V
• Input Logic Levels
  • VIL = 0.8V Max
  • VIH = VCC/2 Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay 25ns (Max), 16ns (Typ)