HCTS646MS
Rad-Hard Octal Bus Transceiver/Register, Three-State

Key Features

• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm²/mg
• Single Event Upset (SEU) Immunity < 2 x 10^-9 Errors/ Bit-Day (Typ)
• Dose Rate Survivability: >1 x 10¹² RAD (Si)/s
• Dose Rate Upset >10¹⁰ RAD (Si)/s 20ns Pulse
• Cosmic Ray Upset Rate 2 x 10^-9 Errors/Bit Day
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Bus Driver Outputs - 15 LSTTL Loads
• Military Temperature Range: -55^oC to +125^oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• VIL = 0.8V Max
• VIH = VCC/2
• Input Current Levels Ii ≤ 5µA at VOL, VOH

Description

The Intersil HCTS646MS is a Radiation Hardened Three- State Octal Bus Tranceiver/Register with Non-Inverting outputs. This device is a bus transceiver with D-type flip-flops which act as internal storage registers. Data on the A bus or the B bus can be clocked into the registers on a High-to-Low transition of either CAB ro CBA clock inputs. Output enable (OE) and Direction (DIR) inputs control the transceiver functions. Data present at the high impedance output can be stored in either register or both but only one of the two buses can be enabled as outputs at any one time. The select controls (SAB and SBA) can multiplex stored and transparent (real time) data. The direction control determines which data bus will receive data when the OE pin is LOW. In the high impedance mode (OE high), A data can be stored in one register and B data in the other register. Data at the A or B terminals can be clocked into the storage flip-flops at any time. The HCTS646MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS646MS is supplied in a 24 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).