ACTS630MS
Rad-Hard EDAC (Error Detection and Correction)

Key Features

• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96721 and Intersil's QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10^-10 Errors/Bit/Day (Typ)
• SEU LET Threshold >100 MEV-cm²/mg
• Dose Rate Upset >10¹¹ RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability >10¹² RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range -55^oC to +125^oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range 4.5V to 5.5V
• Input Logic Levels
• VIL = 0.8V Max
• VIH = VCC/2 Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay 37ns (Max), 24ns (Typ)

Description

The Intersil ACTS630MS is a Radiation Hardened 16-bit parallel error detection and correction circuit. It uses a modified Hamming code to generate a 6-bit check word from each 16-bit data word. The check word is stored with the data word during a memory write cycle; during a memory read cycle a 22-bit word is taken form memory and checked for errors. Single bit errors in the data words are flagged and corrected. Single bit errors in check words are flagged but not corrected. The position of the incorrect bit is pinpointed, in both cases, by the 6-bit error syndrome code which is output during the error correction cycle.

The ACTS630MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic Family.

The ACTS630MS is supplied in a 28 lead Ceramic Flatpack (K suffix) or a 28 Lead Ceramic Dual-In-Line Package (D suffix).