ISL6455A
0.6A PWM Regulator and Dual 0.3A LDOs and Reset
Typical Diagram
Key Features
- Fully integrated synchronous buck regulator + dual LDO
- PWM output voltage adjustable.
- 0.8V to 2.5V with ISL6455 (VIN = 3.3V)
- 0.8V to 3.3V with ISL6455A (VIN = 5.0V)
- High output current 600mA
- Dual LDO adjustable options
- LDO1, 1.2V to VIN-0.3V (3.3Vmax) 300mA
- LDO2, 1.2V to VIN-0.3V (3.3Vmax) 300mA
- Ultra-compact DC/DC converter design
- Stable with small ceramic output capacitors and no load
- High conversion efficiency
- Low shutdown supply current
- Low dropout voltage for LDOs
- LDO1 150mV (typical) at 300mA
- LDO2 150mV (typical) at 300mA
- Low output voltage noise
- <30µVRMS (typical) for LDO2 (VCO supply)
- PG_LDO and PG_PWM (PWM and LDO) outputs
- Extensive circuit protection and monitoring features
- PWM overvoltage protection
- Overcurrent protection
- Shutdown
- Thermal shutdown
- Integrated RESET output for microprocessor reset
- Proven reference design for total WLAN system solution
- QFN package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline
- Near Chip-Scale package footprint Improves PCB efficiency and is thinner in Profile
- Pb-free plus anneal available (RoHS compliant)
Description
The ISL6455 is a highly integrated triple output regulator which provides a single chip solution for FPGAs and wireless chipset power management. The device integrates a high efficiency synchronous buck regulator (adjustable) with two ultra low noise LDO regulators (adjustable). Either the ISL6455 or ISL6455A can be selected based on whether 3.3V ±10% or 5V ±10% is required as an input voltage.
The synchronous current mode control PWM regulator with integrated N- and P-channel power MOSFET provides adjustable voltages based on external resistor setting. Synchronous rectification with internal MOSFETs is used to achieve higher efficiency and reduced number of external components. Operating frequency is typically 750kHz allowing the use of smaller inductor and capacitor values. The device can be synchronized to an external clock signal in the range of 500kHz to 1MHz. The PG_PWM output indicates loss of regulation on PWM output.
The ISL6455 also has two LDO adjustable regulators using internal PMOS transistors as pass devices. LDO2 features ultra low noise typically below 30µVRMS to aid VCO stability. The EN_LDO pin controls LDO1 and LDO2 outputs. The ISL6455 also integrates a RESET function, which eliminates the need for additional RESET IC required in WLAN and other applications. The IC asserts a RESET signal whenever the VIN supply voltage drops below a preset threshold, keeping it asserted for at least 25ms after VIN has risen above the reset threshold. The PG_LDO output indicates loss of regulation on either of the two LDO outputs. Other features include overcurrent protection and thermal shutdown for all the three outputs.
High integration and the thin Quad Flat No-lead (QFN) package makes ISL6455 an ideal choice for powering FPGAs and small form factor wireless cards such as PCMCIA, mini-PCI and Cardbus-32.
Applications
- WLAN cards
- PCMCIA, Cardbus32, MiniPCI cards
- Compact flash cards
- Hand-held instruments
