Applications

Datasheet

ISL6548
ACPI Regulator/Controller for Dual Channel DDR Memory Systems

Typical Diagram

enlarge +typical diagram

Key Features

    • Generates 4 Regulated Voltages
      • Synchronous Buck PWM Controller for DDR VDDQ
      • 3A Integrated Sink/Source Linear Regulator with Accurate VDDQ/2 Divider Reference for DDR VTT
      • LDO Regulator for GMCH Core
      • Sink/Source LDO Regulator for CPU/GMCH VTT Termination
    • ACPI Compliant Sleep State Control
    • Glitch-free Transitions During State Changes
    • PWM Controller Drives Low Cost N-Channel MOSFETs
    • 250kHz Constant Frequency Operation
    • Tight Output Voltage Regulation
      • All Outputs: ±2% Over Temperature
    • Fully-Adjustable Outputs with Wide Voltage Range: Down to 0.8V supports DDR and DDR2 Specifications
    • Simple Single-Loop Voltage-Mode PWM Control Design
    • Fast PWM Converter Transient Response
    • Under and Overvoltage Monitoring on All Outputs
    • OCP on the Switching Regulator
    • Integrated Thermal Shutdown Protection
    • Pb-Free Plus Anneal Available (RoHS Compliant)

Description

The ISL6548 provides a complete ACPI compliant power solution for up to 4 DIMM dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller to supply VDDQ during S0/S1 and S3 states. During S0/S1 state, a fully integrated sink-source regulator generates an accurate (VDDQ/2) high current VTT voltage without the need for a negative supply. Two LDO controllers are also integrated for the GMCH core voltage regulation and for the GMCH/CPU VTT termination voltage regulation.

The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltagemode control with fast transient response. The switching regulator provides a maximum static regulation tolerance of ±2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0.8V.

An integrated soft-start feature brings all outputs into regulation in a controlled manner when returning to S0/S1 state from any sleep state. During S0 the VIDPGD signal indicates that the GMCH/CPU VTT termination voltage is within spec and operational.

Each output is monitored for undervoltage events. The switching regulator also has overvoltage and overcurrent protection. Thermal shutdown is integrated.

Applications

    • Single and Dual Channel DDR Memory Power Systems in ACPI compliant PCs
    • Graphics Cards - GPU and Memory Supplies
    • ASIC Power Supplies
    • Embedded Processor and I/O Supplies
    • DSP Supplies

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