X5045
CPU Supervisor with 4k SPI EEPROM

Key Features

• Low V_CC Detection and Reset Assertion
• Four standard reset threshold voltages 4.63V, 4.38V, 2.93V, 2.63V
• Re-program low V_CC reset threshold voltage using special programming sequence.
• Reset signal valid to V_CC = 1V
• Selectable Time Out Watchdog Timer
• Long Battery Life with Low Power Consumption
• <50µA max standby current, watchdog on
• <10µA max standby current, watchdog off
• 4Kbits of EEPROM-1M Write Cycle Endurance
• Save Critical Data with Block Lock™ Memory
• Protect 1/4, 1/2, all or none of EEPROM array
• Built-in Inadvertent Write Protection
• Write enable latch
• Write protect pin
• SPI Interface - 3.3MHz Clock Rate
• Minimize Programming Time
• 16-byte page write mode
• 5ms write cycle time (typical)
• Available Packages
• 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP
• 14 Ld TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)

Description

These devices combine four popular functions, Poweron Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.

Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code.

The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power.

The device's low V_CC detection circuitry protects the user's system from low voltage conditions, resetting the system when V_CC falls below the minimum V_CC trip point. RESET/RESET is asserted until V_CC returns to proper operating level and stabilizes. Four industry standard V_TRIP thresholds are available, however, Intersil's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.

The memory portion of the device is a CMOS Serial EEPROM array with Intersil's block lock protection. The array is internally organized as 512 x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple fourwire bus.

The device utilizes Intersil's proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.

Applications

• Communications Equipment
• Routers, Hubs, Switches
• Set Top Boxes
• Industrial Systems
• Process Control
• Intelligent Instrumentation
• Computer Systems
• Desktop Computers
• Network Servers
• Battery Powered Equipment