Applications

Datasheet

X5001
CPU Supervisor

Typical Diagram

enlarge +typical diagram

Key Features

    • 200ms power-on reset delay
    • Low VCC detection and reset assertion
      • Five standard reset threshold voltages
      • Adjust low VCC reset threshold voltage using special programming sequence
      • Reset signal valid to VCC = 1V
    • Selectable nonvolatile watchdog timer
      • 0.2, 0.6, 1.4 seconds
      • Off selection
      • Select settings through software
    • Long battery life with low power consumption
      • <50µA max standby current, watchdog on
      • <1µA max standby current, watchdog off
    • 2.7V to 5.5V operation
    • SPI mode 0 interface
    • Built-in inadvertent write protection
      • Power-up/power-down protection circuitry
      • Watchdog change latch
    • High reliability
    • Available packages
      • 8 Ld TSSOP
      • 8 Ld SOIC
      • 8 Ld PDIP
    • Pb-free plus anneal available (RoHS compliant)

Description

This device combines three popular functions, Poweron Reset, Watchdog Timer, and Supply Voltage Supervision in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.

The watchdog timer provides an independent protection mechanism for microcontrollers. During a system failure, the device will respond with a RESET signal after a selectable time out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power.

The user's system is protected from low voltage conditions by the device's low VCC detection circuitry. When VCC falls below the minimum VCC trip point, the system is reset. RESET is asserted until VCC returns to proper operating levels and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.

The device utilizes Intersil's proprietary Direct Write™ cell for the watchdog timer control bits and the VTRIP storage element, providing a minimum endurance of 100,000 write cycles and a minimum data retention of 100 years.

Alternatives

Design Tip

What are the MOSFET Driver Dynamics and Current Sense Methods that one needs to be concerned about in PWM Converters?

See More »

Is there somewhere I can find out what simulations and models (e.g. Spice, PSpice, IBIS) are available on your website?

See More »

iSIM Simulator

Select a category to start designing:

Enter design requirements:

Enter design requirements:

Desired Closed Loop Gain:
Desired Min. Bandwidth:

Support | Ask An Expert

Need tech support for a product or design?
(Support FAQs)

Ask »

Follow Us Intersil Wins Outstanding Achievement in Web Development

Find pricing and availability for your part number. Order Parts, Eval Boards and Samples

Contact Sales »

myINTERSIL

Sign in to your account…
Search Orders    
Please Wait...

Toolbar

Simply Smarter