BBT3420
Quad 2.488-3.1875Gbps/Channel Transceiver

Key Features

• Configurable multi-rate transceivers supporting serial data transfer rates of 2.488Gbps to 3.1875Gbps with full-rate and half-rate operations
• Designed for serial backplane applications
• IEEE 802.3ae 10 Gigabit Ethernet compliant
• XAUI, XGMII, and MDC/MDIO interfaces
• 8B/10B Encoder/Decoder per channel with selectable parallel input/output data sizes
• Single-ended/differential input Reference clock
• Integrated Receiver Equalization and Transmitter Pre-emphasis
• Channel-to-Channel Alignment (optional)
• Programmable Comma detection byte alignment
• Per Channel signal detect indicator
• XGMII supports HSTL 1.8V and 2.5V SSTL_2 with on-chip 25W series output terminations
• Integrated BIST and IEEE 1149.1 JTAG
• 3.3V tolerant I/Os
• Low power, 250mW per channel typical
• Standard 0.18µm 1.8V CMOS process
• 289 ball, 19 mm HSBGA Package
• 2kV ESD protection on all pins

Description

In normal operation, the BBT3420 transmitters accept data from the parallel data bus, clocked by the appropriate Transmit Byte Clock for the channel, and resynchronize it into the Transmit FIFO using the local reference clock. The data is then optionally encoded using the standard 8B/10B encoder, serialized, and sent out on the differential CML, XAUI-compatible transmit pins. The BBT3420 receivers accept serial data from the CML receive pins, perform clock and data recovery on the bit stream, scan the data for the Comma patterns, Byte-Aligns the data on either disparity of the sync pattern, and de-serializes the data. The data is then optionally 8B/10B decoded and fed into the receiver FIFO, where clock compensation, optional channel alignment, and resynchronization to any one of the individual recovered clocks, one channel clock, or the local reference clock are performed. In addition, several other features are provided to ease system testing. Loopback at either the serial or parallel ports is available under external pin or MDIO control. Suitable control and status registers are available through the IEEE standard MDIO/MDC system. The XGMII interface can be configured in source-centered or source synchronous timing formats for ASIC-friendly timing.

If the Built-in-Self-Test function (BIST) is in use, the serial transmit data is instead driven from a PRBS 2²³ -1 pattern generator. In the BIST mode, the received serial data is checked against the PRBS pattern transmitted and, if an error is found, a flag signal is provided.

Applications

The nPower BBT3420 is a quad 8-bit/10-bit parallel-to-serial and serial-to-parallel transceiver device ideal for high bandwidth interconnection between line cards, serial backplanes, or optical modules. In addition to the multi-rate highbandwidth 2.488Gbps to 3.2Gbps links at full-rates and half-rates, the transceivers can be configured as a single 10 Gigabit eXtended Attachment Unit Interface (XAUI), providing up to 12.75 GBdps of duplex bandwidth.