News & Events
Intersil High Speed ADC Webinar
WHEN: Apr 23, 2013
WHERE: Online Webinar
Date: 4/23
Time: 3pm GMT (4pm CET)
On April 23rd, Intersil will present a High Speed ADC Webinar. This webinar will provide the attendees with a better understanding of how the JESD204B high speed serial interface standard can be used in their next design.
Online registration is available at:
http://www.avnet-memec.eu/events/seminar-detail/event/intersil-high-speed-signal-design-webinar.html
AGENDA
- Introduction
- JESD204 Basics
- Features
- Benefits
- Block Diagram of JESD204B System
- Key signal names
- Device Subclass description
- Link Setup
- Design Considerations
- Packing Mode Definitions, Link Parameters
- Serial Line Rate Calculations
- Serial Rate vs. BER tradeoff
- FPGA Design Options
- PCB Design Guide
- System Examples
- Multi-device synchronization using Intersil JESD204B evaluation kit
- Optical Data Transfer using Avago Fiber-optic Trasnceivers and Intersil JESD204B evaluation kit
- Summary & Wrap-up
PRESENTER |
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Edward Kohler Strategic Marketing Manager, Intersil Ed is Intersil’s Strategic Marketing Manager for data converters and ADC drivers. He has eight years of mixed-signal design experience focusing on high speed analog-to-digital converters. He earned his Bachelor’s and Master’s degrees in electrical engineering at Michigan Technological University and the University of Michigan and his MBA from Yale University. |
