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| Programmable Downconverter |
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Available in RoHS/Pb-Free
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 Buy direct from Intersil
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 Check distributor inventory
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 Request samples
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Part No. |
Design-In
Status |
Temp. |
Package |
MSL |
Price
US $ |
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| HSP50214BVC |
Active |
Comm |
120 Ld MQFP |
4 |
58.24 |
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| HSP50214BVCZ |
Active |
Comm |
120 Ld MQFP |
3 |
58.24 |
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| HSP50214BVI |
Active |
Ind |
120 Ld MQFP |
4 |
73.49 |
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| HSP50214BVIZ |
Active |
Ind |
120 Ld MQFP |
3 |
73.49 |
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| The price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. However, prices in today's market are fluid and may change without notice. |
| MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020 |
| SMD = Standard Microcircuit Drawing |
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 Description |
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The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The Programmable Downconverter (PDC) performs down conversion, decimation, narrowband low pass filtering, gain scaling, resampling, and Cartesian to Polar coordinate conversion.
The 14-bit sampled IF input is down converted to baseband by digital mixers and a quadrature NCO, as shown in the Block Diagram. A decimating (4 to 32) fifth order Cascaded Integrator-Comb (CIC) filter can be applied to the data before it is processed by up to 5 decimate-by-2 halfband filters. The halfband filters are followed by a 255-tap programmable FIR filter. The output data from the programmable FIR filter is scaled by a digital AGC before being re-sampled in a polyphase FIR filter. The output section can provide seven types of data: Cartesian (I, Q), polar (R, θ), filtered frequency (dθ/dt), Timing Error (TE), and AGC level in either parallel or serial format. |
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 Key Features |
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Up to 65MSPS Front-End Processing Rates (CLKIN) and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous
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Processing Capable of >100dB SFDR
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Up to 255-Tap Programmable FIR
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Overall Decimation Factor Ranging from 4 to 16384
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Output Samples Rates to ≈ 12.94MSPS with Output Bandwidths to ≈ 982kHz Lowpass
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32-Bit Programmable NCO for Channel Selection and Carrier Tracking
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Digital Resampling Filter for Symbol Tracking Loops and Incommensurate Sample-to-Output Clock Ratios
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Digital AGC with Programmable Limits and Slew Rate to Optimize Output Signal Resolution; Fixed or Auto Gain Adjust
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Serial, Parallel, and FIFO 16-Bit Output Modes
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Cartesian to Polar Converter and Frequency Discriminator for AFC Loops and Demodulation of AM, FM, FSK, and DPSK
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Input Level Detector for External I.F. AGC Support
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Pb-Free Plus Anneal Available (RoHS Compliant)
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| Related Documentation |
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 Application Note(s): |
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 Datasheet(s): |
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 Technical Brief(s): |
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 Evaluation Board(s): |
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 Technical Homepage: |
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 Parametric Data |
| | Clock (MHz) | | 65MHz CLKIN 55MHz PROCCLK (Back End) | | | Data (Bits) | | 14 | | | Decimation Factors | | 4 to 16,384 | | | Filtering | | Fixed CIC Fixed Halfband Programmable FIR Fixed Re-Sampler | |
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| Applications |
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- Single Channel Digital Software Radio Receivers
- Base Station Rx’s: AMPS, NA TDMA, GSM, and CDMA
- Compatible with HSP50210 Digital Costas Loop for PSK Reception
- Evaluation Platform Available
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| | HSP50016 | | Digital Down Converter | | | | HSP50210 | | Digital Costas Loop | | | | HSP50216 | | Four-Channel Programmable Digital DownConverter | | | | ISL5216 | | Four-Channel Programmable Digital DownConverter | | | | ISL5416 | | Four-Channel Wideband Programmable DownConverter | |
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