The HD-4702 Bit Rate Generator provides the necessary clock
signals for digital data transmission systems, such as a UART. It
generates 13 commonly used bit rates using an on-chip crystal
oscillator or an external input. For conventional operation generating
16 output clock pulses per bit period, the input clock frequency
must be 2.4576MHz (i.e. 9600 Baud x 16 x 16, since
there is an internal ÷ 16 prescaler). A lower input frequency will
result in a proportionally lower output frequency.
The HD-4702 can provide multi-channel operation with a minimum
of external logic by having the clock frequency CO and the
÷ 8 prescaler outputs Q0, Q1, Q2 available externally. All signals
have a 50% duty cycle except 1800 Baud, which has less than
0.39% distortion.
The four rate select inputs (S0-S3) select which bit rate is at the
output (Z). See Truth Table for Rate Select Inputs for select code
and output bit rate. Two of the 16 select codes for the HD-4702 do
not select an internally generated frequency, but select an input
into which the user can feed either a different frequency, or a
static level (High or Low) to generate “ZERO BAUD”.
The bit rates most commonly used in modern data terminals
(110, 150, 300, 1200, 2400 Baud) require that no more than one
input be grounded for the HD-4702, which is easily achieved with
a single 5-position switch.
The HD-4702 has an initialization circuit which generates a master
reset for the scan counter. This signal is derived from a digital
differentiator that senses the first high level on the CP input after
the ECP input goes low. When ECP is high, selecting the crystal
input, CP must be low. A high level on CP would apply a continuous
reset. See Clock Modes and Initialization below. |
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